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features: fast detect correct ?idt49c460e 10ns (max.) 14ns (max.) ?idt49c460d 12ns (max.) 18ns (max.) ?idt49c460c 16ns (max.) 24ns (max.) ?idt49c460b 25ns (max.) 30ns (max.) ?idt49c460a 30ns (max.) 36ns (max.) ?idt49c460 40ns (max.) 49ns (max.) low-power cmos ?commercial: 95ma (max.) ?military: 125ma (max.) improves system memory reliability ?corrects all single bit errors, detects all double and some triple-bit errors cascadable ?data words up to 64-bits built-in diagnostics ?capable of verifying proper edc operation via software control simplified byte operations ?fast byte writes possible with separate byte enables functional replacement for 32- and 64-bit configurations of the am29c60 and am29c660 available in pga, plcc and fine pitch flatpack military product compliant to mil-std-883, class b standard military drawing #5962?8533 integrated device technology, inc. military and commercial temperature ranges august 1995 1995 integrated device technology, inc. 11.6 dsc-9017/8 32-bit cmos error detection and correction unit the idt logo is a registered trademark of integrated device technology, inc. description: the idt49c460s are high-speed, low-power, 32-bit error detection and correction units which generate check bits on a 32-bit data field according to a modified hamming code and correct the data word when check bits are supplied. the idt49c460s are performance-enhanced functional replace- ments for 32-bit versions of the 2960. when performing a read operation from memory, the idt49c460s will correct 100% of all single bit errors and will detect all double bit errors and some triple bit errors. the idt49c460s are easily cascadable to 64-bits. thirty- two-bit systems use 7 check bits and 64-bit systems use 8 check bits. for both configurations, the error syndrome is made available. the idt49c460s incorporate two built-in diagnostic modes. both simplify testing by allowing for diagnostic data to be entered into the device and to execute system diagnostics functions. they are fabricated using a cmos technology designed for high-performance and high-reliability. the devices are pack- aged in a 68-pin ceramic pga, plcc and ceramic quad flatpack. military grade product is manufactured in compliance with the latest revision of mil-std-883, class b, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. 1 functional block diagram data latch error correct error decode mux data latch check bit generate mux mux check bit in latch diagnostic latch syndrome generate error detect control logic mux 8 8 8 5 8 8 8 32 32 4 32 13 cb 0? data 0?1 oe byte 0C3 le in le diag le out / generate correct code id 1,0 diag mode 1,0 sc 0C7 oe sc error mult error 2584 drw 01 idt49c460 idt49c460a idt49c460b idt49c460c idt49c460d idt49c460e
11.6 2 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges pin configurations plcc topview 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 98 76 54 32 16867666564636261 d 24 d 23 d 22 d 21 d 20 d 19 d 18 d 17 v cc d 16 oe 2 le out / generate correct le diag error mult error gnd d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 d 12 d 13 d 14 d 15 oe1 v cc gnd j68C1 designates pin 1 for plcc only cb 6 cb 5 cb 4 cb 3 cb 2 cb 1 cb 0 sc 1 sc 2 sc 3 sc 4 sc 5 sc 6 sc 7 oe sc cb 7 sc 0 d 1 d 0 oe 0 le in diag mode 1 diag mode 0 code id 1 code id 0 oe 3 d 31 d 30 d 28 d 27 d 26 d 25 gnd d 29 2584 drw 02
11.6 3 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges fine pitch flatpack topview 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 98 76 54 32 1 68 67 66 65 64 63 62 61 f68 - 2 pin 1 identification d 24 d 23 d 22 d 21 d 20 d 19 d 18 d 17 v cc d 16 oe 2 le out / generate correct le diag error mult error gnd d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 d 12 d 13 d 14 d 15 oe 1 v cc gnd cb 6 cb 5 cb 4 cb 3 cb 2 cb 1 cb 0 sc 1 sc 2 sc 3 sc 4 sc 5 sc 6 sc 7 oe sc cb 7 sc 0 d 1 d 0 diag mode 1 oe 0 le in diag mode 0 code id 1 code id 0 oe 3 d 31 d 30 d 28 d 27 d 26 d 25 gnd d 29 2584 drw 03
11.6 4 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges 51 52 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 17 1 2 34 53 32 33 55 54 30 31 57 56 28 29 59 58 26 27 61 60 24 25 63 62 22 23 65 64 20 21 67 66 68 19 d 25 d 27 d 26 d 29 d 28 d 31 d 30 code id 0 oe 3 diag mode 0 code id 1 le in diag mode 1 d 0 oe 0 d 1 oe sc sc 7 sc 6 sc 5 sc 4 sc 3 sc 2 sc 1 sc 0 cb 0 cb 1 cb 2 cb 3 cb 4 cb 5 cb 6 g68 C 1 d 23 d 22 d 21 d 20 d 19 d 18 d 17 v cc d 16 oe 2 le out / generat e correct le diag error mult error gnd gnd d 24 d 3 d 4 d 5 d 6 d 7 d 8 gnd d 9 d 10 d 11 d 12 d 13 d 14 d 15 cb 7 oe 1 d 2 v cc 2584 drw 04 pga topview
11.6 5 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges pin descriptions pin name i/o description data 0C31 i/o 32 bidirectional data lines provide input to the data input latch and diagnostic latch and also receive output from the data output latch. data 0 is the lsb; data 31 is the msb. cb 0C7 i eight check bit input lines input check bits for error detection and also used to input syndrome bits for error correction in 64-bit applications. le in i latch enable is for the data input latch. controls latching of the input data. data input latch and check bit input latch are latched to their previous state when low. when high, the data input latch and check bit input latch follow the input data and input check bits. le out / generate a multifunction pin which, when low, is in the check bit generate mode. in this mode, the device generates the check bits or generate partial check bits specific to the data in the data input latch. the generated check bits are placed on the sc outputs. also, when low, the data out latch is latched to its previous state. when high, the device is in the detect or correct mode. in this mode, the device detects single and multiple errors and generates syndrome bits based upon the contents of the data input latch and check bit input latch. in the correct mode, single bit errors are also automatically corrected and the corrected data is placed at the inputs of the data output latch. the syndrome result is placed on the sc outputs and indicates in a coded form the number of errors and the specific bit-in-error. when high, the data output latch follows the output of the data input latch as modified by the correction logic network. in correct mode, single bit errors are corrected by the network before being loaded into the data output latch. in detect mode, the contents of the data input latch are passed through the correction network unchanged into the data output latch. the data output latch is disabled, with its contents unchanged, if the edc is in the generate mode. sc 0C7 o syndrome check bit outputs. eight outputs which hold the check bits and partial check bits when the edc is in the generate mode and will hold the syndrome/partial syndrome bits when the device is in the detect or correct modes. all are 3-state outputs. oe sc i output enablesyndrome check bits. in the high condition, the sc outputs are in the high impedance state. when low, all sc output lines are enabled. error o in the detect or correct mode, this output will go low if one or more data or check bits contain an error. when high, no errors have been detected. this pin is forced high in the generate mode. mult error o in the detect or correct mode, this output will go low if two or more bit errors have been detected. a high level indicates that either one or no errors have been detected. this pin is forced high in the generate mode. correct i the correct input which, when high, allows the correction network to correct any single-bit error in the data input latch (by complementing the bit-in-error) before putting it into the data output latch. when low, the device will drive data directly from the data input latch to the data output latch without correction. oe byte 0C3 i output enablebytes 0, 1, 2, 3. data output latch. control the three-state output buffers for each of the four bytes of the data output latch. when low, they enable the output buffer of the data output latch. when high, they force the data output latch buffer into the high impedance mode. one byte of the data output latch is easily activated by separately selecting the four enable lines. diag mode 1,0 i select the proper diagnostic mode. they control the initialization, diagnostic and normal operation of the edc. code id 1,0 i these two code identification inputs identify the size of the total data word to be processed. the two allowable data word sizes are 32 and 64 bits and their respective modified hamming codes are designated 32/39 and 64/72. special code id 1,0 , input 01 is also used to instruct the edc that the signals code id 1,0 , diag mode 1,0 and correct are to be taken from the diagnostic latch rather than from the input control lines. le diag i this is the latch enable for the diagnostic latch. when high, the diagnostic latch follows the 32-bit data on the input lines. when low, the outputs of the diagnostic latch are latched to their previous states. the diagnostic latch holds diagnostic check bits and internal control signals for code id 1,0 , diag mode 1,0 and correct. 2584 tbl 01
11.6 6 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges edc architecture summary the idt49c460s are high-performance cascadable edcs used for check bit generation, error detection, error correction and diagnostics. the function blocks for this 32-bit device consist of the following: ? data input latch ? check bit input latch ? check bit generation logic ? syndrome generation logic ? error detection logic ? error correction logic ? data output latch ? diagnostic latch ? control logic data input/output latch the latch enable input, le in , controls the loading of 32 bits of data to the data in latch. the data from the data lines can be loaded in the diagnostic latch under control of the diagnostic latch enable, le diag , giving check bit information in one byte and control information in another byte. the diagnostic latch is used in the internal control mode or in one of the diagnostic modes. the data output latch has buffers that place data on the data lines. these buffers are split into four 8-bit buffers, each having their own output enable con- trols. this feature facilitates byte read and byte modify operations. check bit generation logic this generates the appropriate check bits for the 32 bits of data in the data input latch. the modified hamming code is the basis for generating the proper check bits. syndrome generation logic in both the detect and correct modes, this logic does a comparison on the check bits read from memory against the newly generated set of check bits produced for the data read in from memory. matching sets of check bits mean no error was detected. if there is a mismatch, one or more of the data or check bits is in error. syndrome bits are produced by an exclusive-or of the two sets of check bits. identical sets of check bits mean the syndrome bits will be all zeros. if an error results, the syndrome bits can be decoded to determine the number of errors and the specific bit-in-error. error detection logic this part of the device decodes the syndrome bits generated by the syndrome generation logic. with no errors in either the input data or check bits, both the error and multerror outputs are high. error will go low if one error is detected. multerror and error will both go low if two or more errors are detected. error correction logic in single error cases, this logic complements (corrects) the single data bit-in-error. this corrected data is loaded into the data output latch, which can then be read onto the bidirec- tional data lines. if the error is resulting from one of the check bits, the correction logic does not place corrected check bits on the syndrome/check bit outputs. if the corrected check bits are needed, the edc must be switched to the generate mode. data output latch and output buffers the data output latch is used for storing the result of an error correction operation. the latch is loaded from the correction logic under control of the data output latch en- able, le out . the data output latch may also be directly loaded from the data input latch in the passthru mode. the data output latch buffer is split into 4 individual buffers which can be enabled by oe 0C3 separately for reading onto the bidirectional data lines. diagnostic latch the diagnostic latch is loadable under control of the diagnostic latch enable, le diag , from the bidirectional data lines. check bit information is contained in one byte while the other byte contains the control information. the diagnostic latch is used for driving the device when in the internal control mode, or for supplying check bits when in one of the diagnostic modes. control logic specifies in which mode the device will be operating in. normal operation is when the control logic is driven by external control inputs. in the internal control mode, the control signals are read from the diagnostic latch. since le out and generate are controlled by the same pin, the latching action (le out from high to low) of the data output latch causes the edc to go into the generate mode.
11.6 7 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges detailed product description the idt49c460 edc units contain the logic necessary to generate check bits on 32 bits of data input according to a modified hamming code. the edc can compare internally generated check bits against those read with the 32-bit data to allow correction of any single bit data error and detection of all double (and some triple) bit errors. the idt49c460s can be used for 32-bit data words (7 check bits) and 64-bit (8 check bits) data words. word size selection the two code identification pins, code id 1, 0 , are used to determine the data word size that is 32 or 64 bits. they also select the internal control mode. table 4 defines all possible slice identification codes. check and syndrome bits the idt49c460s provide either check bits or syndrome bits on the three-state output pins, sc 0C7 . check bits are generated from a combination of the data input bits, while syndrome bits are an exclusive-or of the check bits gener- ated from read data with the read check bits stored with the data. syndrome bits can be decoded to determine the single bit in error or that a double (some triple) error was detected. the check bits are labeled: c 0 , c 1 , c 2 , c 3 , c 4 , c 5 , c 6 for the 32-bit configuration c 0 , c 1 , c 2 , c 3 , c 4 , c 5 , c 6 , c 7 for the 64-bit configuration syndrome bits are similarly labeled s 0 through s 7 . 2584 tbl 02 table 2. diagnostic mode control notes: 2584 tbl 03 1. in generate mode, data is read into the edc unit and the check bits are generated. the same data is written to memory along with the check bits. since the data out latch is not used in the generate mode, le out (being low since it is tied to generate) does not affect the writing of check bits. 2. error dep (error dependent): error will be low for single or multiple errors, with mult error low for double or multiple errors. both signals are high for no errors. 3. le in is low. table 3. idt49c460 operating modes correct diag mode 0 diag mode 1 diagnostic mode selected x00 non-diagnostic mode. normal edc function in this mode. x01 diagnostic generate. the con tents of the diagnostic latch are substituted for the normally generated check bits when in the generate mode. the edc functions normally in the detect or correct modes. 0/1 1 0 diagnostic detect/correct. in either mode, the contents of the diagnostic latch are substituted for the check bits normally read from the check bit input latch. the edc functions normally in the generate mode. 111 initialize. the data input latch outputs are forced to zeros and latched upon removal of initialize mode. 011 passthru. operating mode dm 0 dm 1 generate correct data out latch sc 0? ( oe oe sc = low) error error mult error mult error generate 0 1 0 0 0xle out = low (1) check bits generated from data in latch high detect 0 0 0 1 1 0 data in latch syndrome bits data in / check bit latch error dep (2) correct 0 0 0 1 1 1 data in latch w/ single bit correction syndrome bits data in / check bit latch error dep passthru 1 1 1 0 data in latch check bit latch high diagnostic generate 0 1 0 x check bits from diagnostic latch high diagnostic detect 1 0 1 0 data in latch syndrome bits data in / diagnostic latch error dep diagnostic correct 1 0 1 1 data in latch w/ single bit correction syndrome bits data in / diagnostic latch error dep initialization 1 1 1 1 data in latch set to 0000 (3) internal code id 1,0 = 01 (control signals code id 1,0 , diag mode 1,0 and correct are taken from diagnostic latch.)
11.6 8 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges operating mode selection tables 2 and 3 describe the nine operating modes of the idt49c460s. the diagnostic mode pins diag mode 0,1 define four basic areas of operation. generate and correct further divide operation into 8 functions, with code id 1,0 defining the ninth mode as the internal mode. generate mode is used to display the check bits on the outputs sc 0C7 . the diagnostic generate mode displays check bits as stored in the diagnostic latch. detect mode provides an indication of errors or multiple errors on the outputs error and mult error . single bit errors are not corrected in this mode. the syndrome bits are provided on the outputs sc 0C7 . for the diagnostic detect mode, the syndrome bits are generated by comparing the internally generated check bits from the data in latch with check bits stored in the diagnostic latch rather than with the check bit latch contents. correct mode is similar to the detect mode except that single bit errors will be complemented (corrected) and made available as input to the data out latches. again, the diagnostic correct mode will correct single bit errors as determined by syndrome bits generated from the data input and contents of the diagnostic latches. the initialize mode provides check bits for all zero bit data. data input latches are set, latched to a logic zero and made available as input to the data out latches. the internal mode disables the external control pins diag mode 0,1 and correct to be defined by the diagnostic latch. even code id 1,0 , although externally set to the 01 code, can be redefined from the diagnostic latch data. code id 1 code id 0 slice selected 0 0 32-bit 0 1 internal control mode 1 0 64-bit, lower 32Cbit (0C31) 1 1 64-bit, upper 32-bit (32C63) 2584 tbl 04 table 4. slice identification data 0C31 data 0C31 cb 7 high cb 6 c 6 cb 5 c 5 cb 4 c 4 cb 3 c 3 cb 2 c 2 cb 1 c 1 cb 0 c 0 sc 7 nc sc 6 s 6 /c 6 sc 5 s 5 /c 5 sc 4 s 4 /c 4 sc 3 s 3 /c 3 sc 2 s 2 /c 2 sc 1 s 1 /c 1 sc 0 s 0 /c 0 code id 1,0 idt49c460 0,0 2584 drw 05 figure 1. 32-bit configuration figure 2. 64-bit configuration byte 3 byte 2 byte 1 byte 0 c 0 c 1 c 2 c 3 c 4 c 5 c 6 data check bits 0 7 8 15 16 23 24 31 2584 drw 07 byte 7 byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 data check bits 0 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 2584 drw 08 figure 3. 32-bit data format figure 4. 64-bit data format data 0C31 data 32C63 data input checkCbit inputs 1/8 idt74fct240 data cb 0C7 oe sc code id 1,0 sc 0C7 idt49c460 (lower 32 bits) data cb 0C7 oe sc code id 1,0 sc 0C7 idt49c460 (upper 32 bits) error mult error mult error error syndrome/ check bits 1,1 1,0 oe sc 32 32 8 8 8 2584 drw 06
11.6 9 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges 32-bit data word configuration a single idt49c460 edc unit, connected as shown in figure 1, provides all the logic needed for single bit error correction and double bit error detection of a 32-bit data field. the identification code indicates 7 check bits are required. the cb 7 pin should be high. figure 3 indicates the 39-bit data format for two bytes of data and 7 check bits. table 3 describes the operating mode available. table 6 indicates the data bits participating in the check bit generation. for example, check bit c 0 is the exclusive-or function of the 16 data input bits marked with an x. check bits are generated and output in the generate and initialization mode. check bits from the respective latch are passed, unchanged, in the passthru or diagnostic generate mode. syndrome bits are generated by an exclusive-or or the generated check bits with the read check bits. for example, s n is the xor of check bits c n from those read with those generated. table 7 indicates the decoding of the seven syndrome bits to identify the bit-in-error for a single bit error, or whether a double or triple bit error was detected. the all zero case indicates no errors detected. in the correct mode, the syndrome bits are used to complement (correct) single bit errors in the data bits. for double or multiple error detection, the data available as input to the data out latch is not defined. table 5 defines the bit definition for the diagnostic latch. as defined in table 3, several modes will use the diagnostic check bits to determine syndrome bits or to pass as check bits to the sc 0C7 outputs. the internal mode substitutes the indicated bit position for the external control signals. 2584 drw 05 table 5. 32-bit diagnostic latch coding format bit 0 cb 0 diagnostic bit 1 cb 1 diagnostic bit 2 cb 2 diagnostic bit 3 cb 3 diagnostic bit 4 cb 4 diagnostic bit 5 cb 5 diagnostic bit 6 cb 6 diagnostic bit 7 cb 7 diagnostic bit 8 code id 0 bit 9 code id 1 bit 10 diag mode 0 bit 11 diag mode 1 bit 12 correct bit 13C31 don't care generated participating data bits check bits parity 0123456789101112131415 c 0 even (xor) x x x x x x x x c 1 even (xor) x x x x x x x x c 2 odd (xnor) x x x x x x x x c 3 odd (xnor) x x x x x x x x c 4 even (xor) x x x x x x x x c 5 even (xor) x x x x x x x x c 6 even (xor) xxxx xxxx 2584 tbl 06 table 6. 32?it modified hamming code?heck bit encode chart 2584 tbl 07 generated participating data bits check bits parity 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 c 0 even (xor) x x x x x x x x c 1 even (xor) x x x x x x x x c 2 odd (xnor) x x x x x x x x c 3 odd (xnor) x x x x x x x x c 4 even (xor) x x x x x x x x c 5 even (xor) x x x x x x x x c 6 even (xor) x x x x x x x x
11.6 10 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges table 3 describes the operating modes available for the 64/ 72 configuration. table 11 indicates the data bits participating in the check bit generation. for example, check bit c 0 is the exclusive-or function of the 32 data input bits marked with an x. check bits are generated and output in the generate and initialization modes. check bits are passed as stored in the passthru or diagnostic generate modes. syndrome bits are generated by an exclusive-or of the generated check bits with the read check bits. for example, s n is the xor of check bits c n from those read with those generated. table 9 indicates the decoding of the 8 syndrome bits to determine the bit in error for a single bit error or whether a double or triple bit error was detected. the all zero case indicates no errors detected. in the correct mode, the syndrome bits are used to complement (correct) single bit errors in the data bits. for double or multiple error detection, the data available as input to the data out latch is not defined. tables 8a and 8b define the bit definition for the diagnostic latch. as defined in table 3, several modes will use the diagnostic check bits to determine syndrome bits or to pass as check bits to the sc 0C7 outputs. the internal mode sub- stitutes the indicated bit position for the external control signals. performance data is provided in table 10, relating a single idt49c460 edc with the two cascaded units of figure 2. as indicated, a summation of propagation delays is required from the cascading arrangement of edc units. notes: 2584 tbl 08 1. * = no errors detected 2. number = the number of the single bit-in-error 3. t = two errors detected 4. m = three or more errors detected table 7. syndrome decode to bit-in-error (32-bit) 64-bit data word configuration two idt49c460 edc units, connected as shown in figure 2, provide all the logic needed for single bit error detection and double bit error detection of a 64-bit data field. table 4 gives the code id 1,0 values needed for distinguishing the upper 32 bits from the lower 32 bits. valid syndrome, check bits and the error and mult error signals come from the ic with the code id 1,0 = 11. control signals not indicated are connected to both units in parallel. the edc with the code id 1,0 = 10 has the oe sc grounded. the oe sc selects the syndrome bits from the edc with code id 1,0 = 11 and also controls the check bit buffers from memory. data in bits 0 through 31 are connected to the same numbered inputs of the edc unit with code id 1,0 = 10, while data in bits 32 through 63 are connected to data inputs 0 to 31, respectively, for the edc unit with code id 1,0 = 11. figure 4 indicates the 72-bit data format of 8 bytes of data and 8 check bits. check bits are input to the edc unit with code id 1,0 = 10 through a three-state buffer unit such as the idt74fct244. correction of single bit errors of the 64-bit configuration requires a feedback of syndrome bits from the upper edc unit to the lower edc unit. the mux shown on the functional block diagram is used to select the cb 0C7 pins as the syndrome bits rather than internally generated syndrome bits. 2584 tbl 09 table 8a. 64-bit diagnostic latch?oding format (diagnostic and correct mode) bit internal function 0cb 0 diagnostic 1cb 1 diagnostic 2cb 2 diagnostic 3cb 3 diagnostic 4cb 4 diagnostic 5cb 5 diagnostic 6cb 6 diagnostic 7cb 7 diagnostic 8 code id 0 lower 32-bit 9 code id 1 lower 32-bit 10 diag mode 0 lower 32-bit 11 diag mode 1 lower 32-bit 12 correct lower 32-bit 13C31 don't care 32C39 don't care 40 code id 0 upper 32-bit 41 code id 1 upper 32-bit 42 diag mode 0 upper 32-bit 43 diag mode 1 upper 32-bit 44 correct upper 32-bit 45C63 don't care hex 01234567 syndrome s 6 00001111 bits s 5 00110011 s 4 01010101 hex s 3 s 2 s 1 s 0 0 0 0 0 0 * c4 c5 t c6 t t 30 1 0 0 0 1 c0 t t 14 t m m t 20010 c1ttmt224t 30011 t188tmttm 4 0 1 0 0 c2 t t 15 t 3 25 t 50101 t199tmtt31 60110 t2010tmttm 70111 mttmt426t 81000 c3ttmt527t 91001 t2111tmttm a1010 t2212t1ttm b1011 17ttmt628t c1100 t2313tmttm d1101 mttmt729t e1110 16ttmtmmt f1111 tmmt0ttm
11.6 11 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges bit internal function 0C7 don't care 8 code id 0 lower 32-bit 9 code id 1 lower 32-bit 10 diag mode 0 lower 32-bit 11 diag mode 1 lower 32-bit 12 correct lower 32-bit 13C31 don't care 32 cb 0 diagnostic 33 cb 1 diagnostic 34 cb 2 diagnostic 35 cb 3 diagnostic 36 cb 4 diagnostic 37 cb 5 diagnostic 38 cb 6 diagnostic 39 cb 7 diagnostic 40 code id 0 upper 32-bit 41 code id 1 upper 32-bit 42 diag mode 0 upper 32-bit 43 diag mode 1 upper 32-bit 44 correct upper 32-bit 45C63 don't care 2584 tbl 10 table 8b. 64-bit diagnostic latch?oding format (diagnostic and correct mode) hex 01 23 45 67 89abcde f s 7 00 00 00 00 11 11 11 1 1 syndrome s 6 00 00 11 11 00 00 11 1 1 bits s 5 00 11 00 11 00 11 00 1 1 s 4 01 01 01 01 01 01 01 0 1 hex s 3 s 2 s 1 s 0 0 0 0 0 0 * c4 c5 t c6 t t 62 c7 t t 46 t m m t 1 0 0 0 1 c0t t14tmmt tmmt mt t30 20 01 0 c1ttmt3456tt5040tmttm 3 0 0 1 1 t188 t mt tmmt tm t 224t 4 0 1 0 0 c2 t t 15 t 35 57 t t 51 41 t m t t 31 5 0 1 0 1 t 19 9 t m t t 63 m t t 47 t 3 25 t 6 0 1 1 0 t 20 10 t m t t m m t t m t 4 26 t 7 0 1 1 1 m t t m t 36 58 t t 52 42 t m t t m 81 00 0 c3ttmt3759tt5343tmttm 9 1 0 0 1 t 21 11 t m t t m m t t m t 5 27 t a 1 0 1 0 t 22 12 t 33 t t m 49 t t m t 6 28 t b 1 0 1 1 17t tm t3860t t5444t 1 t t m c 1 1 0 0 t 23 13 t m t t m m t t m t 7 29 t d 1 1 0 1 m t t m t 39 61 t t 55 45 t m t t m e 1 1 1 0 16t tm tmmt tmmt 0 t t m f 1 1 1 1 tmmt32t tm48t tm tmm t notes: 2584 tbl 11 * = no errors detected t = two errors detected number = the number of the single bit-in-error m = three or more errors detected table 9. syndrome decode to bit?n?rror (64?it configuration)
11.6 12 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges 2584 tbl 12 table 10. key calculations for the 64?it configuration 64?it propagation delay from to component delay for idt49c460 ac specifications data check bits out (data to sc) + (cb to sc, code id 11) data corrected data out (data to sc) + (cb to sc, code id 11) + (cb to data, code id 10) data syndromes out (data to sc) + (cb to sc, code id 11) data error for 64 bits (data to sc) + (cb to error , code id 11) data mult error for 64 bits (data to sc) + (cb to mult error , code id 11)
11.6 13 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges generated participating data bits check bits parity 0123456789101112131415 c 0 even (xor) x x x x x x x x c 1 even (xor) x x x x x x x x c 2 odd (xnor) x x x x x x x x c 3 odd (xnor) x x x x x x x x c 4 even (xor) x x x x x x x x c 5 even (xor) x x x x x x x x c 6 even (xor) xxxx xxxx c 7 even (xor) xxxx xxxx 2584 tbl 13 generated participating data bits check bits parity 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 c 0 even (xor) x x x x x x x x c 1 even (xor) x x x x x x x x c 2 odd (xnor) x x x x x x x x c 3 odd (xnor) x x x x x x x x c 4 even (xor) x x x x x x x x c 5 even (xor) x x x x x x x x c 6 even (xor) x x x x x x x x c 7 even (xor) x x x x x x x x 2584 tbl 14 generated participating data bits check bits parity 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 c 0 even (xor) x x x x x x x x c 1 even (xor) x x x x x x x x c 2 odd (xnor) x x x x x x x x c 3 odd (xnor) x x x x x x x x c 4 even (xor) x x x x x x x x c 5 even (xor) x x x x x x x x c 6 even (xor) xxxx xxxx c 7 even (xor) x x x x x x x x 2584 tbl 15 generated participating data bits check bits parity 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 c 0 even (xor) x x x x x x x x c 1 even (xor) x x x x x x x x c 2 odd (xnor) x x x x x x x x c 3 odd (xnor) x x x x x x x x c 4 even (xor) x x x x x x x x c 5 even (xor) x x x x x x x x c 6 even (xor) x x x x x x x x c 7 even (xor) xxxx xxxx note: 2584 tbl 16 1. the check bit is generated as either an xor or xnor of the 32 data bits noted by an x in the table. table 11. 64?it modified hamming code?heck bit encoding
11.6 14 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges sc outputs the tables below indicate how the sc 0C7 outputs are generated in each control mode of various code ids (internal control mode not applicable). correct/ code id 1,0 detect 00 10 11 sc 0 ? ph0 ? c 0 ph1 ? c 0 ph2 ? cb 0 sc 1 ? pa ? c 1 pa ? c 1 pa ? cb 1 sc 2 ? pb ? c 2 pb ? c 2 pb ? cb 2 sc 3 ? pc ? c 3 pc ? c 3 pc ? cb 3 sc 4 ? pd ? c 4 pd ? c 4 pd ? cb 4 sc 5 ? pe ? c 5 pe ? c 5 pe ? cb 5 sc 6 ? pf ? c 6 pf ? c 6 pf ? cb 6 sc 7 ? pf ? c 7 pg ? cb 7 final syndrome partial syndrome final syndrome 2584 tbl 17 2584 tbl 19 code id 1,0 generate 00 10 11 sc 0 ? ph0 ph1 ph2 ? cb 0 sc 1 ? pa pa pa ? cb 1 sc 2 ? pb pb pb ? cb 2 sc 3 ? pc pc pc ? cb 3 sc 4 ? pd pd pd ? cb 4 sc 5 ? pe pe pe ? cb 5 sc 6 ? pf pf pf ? cb 6 sc 7 ? pfpg ? cb 7 final check bits partial check bits final check bits diagnostic correct/ code id 1,0 detect 00 10 11 sc 0 ? ph0 ? dl0 ph1 ? dl0 ph2 ? cb 0 sc 1 ? pa ? dl1 pa ? dl1 pa ? cb 1 sc 2 ? pb ? dl2 pb ? dl2 pb ? cb 2 sc 3 ? pc ? dl3 pc ? dl3 pc ? cb 3 sc 4 ? pd ? dl4 pd ? dl4 pd ? cb 4 sc 5 ? pe ? dl5 pe ? dl5 pe ? cb 5 sc 6 ? pf ? dl6 pf ? dl6 pf ? cb 6 sc 7 ? pf ? dl7 pg ? cb 7 final syndrome partial syndrome final syndrome diagnostic code id 1,0 generate 00 10 11 sc 0 ? dl0 dl0 dl32 sc 1 ? dl1 dl1 dl33 sc 2 ? dl2 dl2 dl34 sc 3 ? dl3 dl3 dl35 sc 4 ? dl4 dl4 dl36 sc 5 ? dl5 dl5 dl37 sc 6 ? dl6 dl6 dl38 sc 7 ? dl7 dl39 final check bits partial check bits final check bits 2584 tbl 20 2584 tbl 18 code id 1,0 passthru 00 10 11 sc 0 ? c0 c0 cb 0 sc 1 ? c1 c1 cb 1 sc 2 ? c2 c2 cb 2 sc 3 ? c3 c3 cb 3 sc 4 ? c4 c4 cb 4 sc 5 ? c5 c5 cb 5 sc 6 ? c6 c6 cb 6 sc 7 ? c7 cb 7 2584 tbl 21 table 12. sc0-7 outputs for different control modes
11.6 15 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges functional equations the equations below describe the idt49c460 output val- ues as defined by the value of the inputs and internal states. definitions pa = d 0 ? d 1 ? d 2 ? d 4 ? d 6 ? d 8 ? d 10 ? d 12 ? d 16 ? d 17 ? d 18 ? d 20 ? d 22 ? d 24 ? d 26 ? d 28 pb = d 0 ? d 3 ? d 4 ? d 7 ? d 9 ? d 10 ? d 13 ? d 15 ? d 16 ? d 19 ? d 20 ? d 23 ? d 25 ? d 26 ? d 29 ? d 31 pc = d 0 ? d 1 ? d 5 ? d 6 ? d 7 ? d 11 ? d 12 ? d 13 ? d 16 ? d 17 ? d 21 ? d 22 ? d 23 ? d 27 ? d 28 ? d 29 pd = d 2 ? d 3 ? d 4 ? d 5 ? d 6 ? d 7 ? d 14 ? d 15 ? d 18 ? d 19 ? d 20 ? d 21 ? d 22 ? d 23 ? d 30 ? d 31 pe = d 8 ? d 9 ? d 10 ? d 11 ? d 12 ? d 13 ? d 14 ? d 15 ? d 24 ? d 25 ? d 26 ? d 27 ? d 28 ? d 29 ? d 30 ? d 31 pf = d 0 ? d 1 ? d 2 ? d 3 ? d 4 ? d 5 ? d 6 ? d 7 ? d 24 ? d 25 ? d 26 ? d 27 ? d 28 ? d 29 ? d 30 ? d 31 pg = d 8 ? d 9 ? d 10 ? d 11 ? d 12 ? d 13 ? d 14 ? d 15 ? d 16 ? d 17 ? d 18 ? d 19 ? d 20 ? d 21 ? d 22 ? d 23 ph0 = d 0 ? d 4 ? d 6 ? d 7 ? d 8 ? d 9 ? d 11 ? d 14 ? d 17 ? d 18 ? d 19 ? d 21 ? d 26 ? d 28 ? d 29 ? d 31 ph1 = d 1 ? d 2 ? d 3 ? d 5 ? d 8 ? d 9 ? d 11 ? d 14 ? d 17 ? d 18 ? d 19 ? d 21 ? d 24 ? d 25 ? d 27 ? d 30 ph2 = d 0 ? d 4 ? d 6 ? d 7 ? d 10 ? d 12 ? d 13 ? d 15 ? d 16 ? d 20 ? d 22 ? d 23 ? d 26 ? d 28 ? d 29 ? d 31 data correction the tables below indicate which data output bits are corrected depending upon the syndromes and the code id 1,0 position. the syndromes that determine data correction are, in some cases, syndromes input externally via the cb inputs and, in some cases, syndromes input externally by that edc (s i are the internal syndromes and are the same as the value of the sc i output of that edc if enabled).
11.6 16 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges absolute maximum ratings (1) capacitance (t a = + 25 c, f = 1.0mhz) symbol rating com'l. mil. unit v term terminal voltage with respect to gnd C0.5 to v cc + 0.5v C0.5 to v cc + 0.5v v v cc power supply voltage -0.5 to +7.0 -0.5 to +7.0 v t a operating temperature 0 to +70 C55 to +125 c t bias temperature under bias C55 to +125 C65 to +135 c t stg storage temperature C55 to +125 C65 to +150 c i out dc output current 30 30 ma symbol parameter (1) conditions typ. unit c in input capacitance v in = 0v 5 pf c out output capacitance v out = 0v 7 pf note: 2584 tbl 25 1. this parameter is sampled and not 100% tested. note: 2584 tbl 24 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics over operating range following conditions apply unless otherwise specified: v lc = 0.2v; v hc = v cc C 0.2v commercial: t a = 0 c to +70 c, v cc = 5.0v 5%; military: t a = C55 c to +125 c, v cc = 5.0v 10% notes: 2584 tbl 26 1. for conditions shown as max. or min. use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at v cc = 5.0v, + 25 c ambient and maximum loading. 3. not more than one output should be shorted at one time. duration of the circuit test should not exceed one second. 4. these input levels provide zero noise immunity and should only be static tested in a noise-free environment. symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level (4) 2.0 v v il input low level guaranteed logic low level (4) 0.8 v i i h input high current v cc = max., v in = v cc 0.1 10.0 m a i i l input low current v cc = max., v in = gnd C0.1 C10.0 m a v oh output high voltage v cc = min. i oh = 300 m av cc v i oh = C12ma mil. 2.4 4.3 i oh = C15ma com'l. 2.4 4.3 v ol output low voltage v cc = min. i ol = 300 m a gnd v i ol = 12ma mil. 0.3 0.5 i ol = 16ma com'l. 0.3 0.5 i oz off state (high impedance) v cc = max. v o = 0v C0.1 C20.0 m a output current v o = v cc (max.) 0.1 20.0 i os output short circuit current v cc = max., v out = 0v (3) C30.0 ma
11.6 17 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges dc electrical characteristics (cont?.) commercial: t a = 0 c to +70 c, v cc = 5.0v 5%; military: t a = C55 c to +125 c, v cc = 5.0v 10% v lc = 0.2v; v hc = v cc C 0.2v symbol parameter test conditions min. typ. max. unit i ccq quiescent power supply current v cc = max.; all inputs 3.0 10 ma (cmos inputs) v hc v in , v in v lc f op = 0; outputs disabled i cct quiescent input power supply v cc = max., v in = 3.4v, f op = 0 0.3 0.75 ma/ current (per input @ ttl high) (5) input i ccd dynamic power supply current v cc = max. mil. 6 10 ma/ v hc v in , v in v lc com'l. 6 7 mhz outputs open, oe = l i cc total power supply current (6) v cc = max., f op = 10mhz mil. 60 110 ma outputs open, oe = l com'l. 60 80 50 % duty cycle v hc v in , v in v lc v cc = max., f op = 10mhz mil. 70 125 outputs open, oe = l com'l. 70 95 50 % duty cycle v ih = 3.4v, v il = 0.4v notes: 2584 tbl 27 5. i cct is derived by measuring the total current with all the inputs tied together at 3.4v, subtracting out i ccq , then dividing by the total number of inputs. 6. total supply current is the sum of the quiescent current and the dynamic current (at either cmos or ttl input levels). for all conditions, the total supply current can be calculated by using the following equation: i cc = i ccq + i cct (n t x d h ) + i ccd (f op ) d h = data duty cycle ttl high period (v in = 3.4v). n t = number of dynamic inputs driven at ttl levels. f op = operating frequency in megahertz. cmos testing considerations special test board considerations must be taken into account when applying high-speed cmos products to the automatic test environment. large output currents are being switched in very short periods and proper testing demands that test set-ups have minimized inductance and guaranteed zero voltage grounds. the techniques listed below will assist the user in obtaining accurate testing results: 1) all input pins should be connected to a voltage potential during testing. if left floating, the device may oscillate, causing improper device operation and possible latchup. 2) placement and value of decoupling capacitors is critical. each physical set-up has different electrical characteristics and it is recommended that various decoupling capacitor sizes be experimented with. capacitors should be positioned using the minimum lead lengths. they should also be distributed to decouple power supply lines and be placed as close as possible to the dut power pins. 3) device grounding is extremely critical for proper device testing. the use of multi-layer performance boards with radial decoupling between power and ground planes is necessary. the ground plane must be sustained from the performance board to the dut interface board and wiring unused interconnect pins to the ground plane is recommended. heavy gauge stranded wire should be used for power wiring, with twisted pairs being recommended for minimized inductance. 4) to guarantee data sheet compliance, the input thresholds should be tested per input pin in a static environment. to allow for testing and hardware-induced noise, idt recommends using v il 0v and v ih 3 3v for ac tests.
11.6 18 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges preliminary note: (15) above applies to correction path. 2584 tbl 71 idt49c460e ac electrical characteristics (guaranteed commercial range performance) temperature range: 0 c to +70 c, v cc = 5.0v 5% the inputs switch between 0v to 3v with signal measured at the 1.5v level. propagation delays (1) set-up and hold times relative to latch enables notes: 2584 tbl 73 1. ci = 50pf. 2. these parameters are combinational propagation delay calculations, and are not tested in production. 3. data in or correct data out measurement requires timing as shown in the switching waveforms. 4. set-up and hold times relative to latch enables (latching data). 5. output tests specified with ci = 5pf and measured to 0.5v change of output level. testing is performed at ci = 50pf and correlated to ci = 5pf. 6. not production tested, guaranteed by characterization. output enable/disable times (5) minimum pulse widths min. le in , le out / generate , le diag ud ud (positiveCgoing pulse) 5 ns enable disable from input enable disable to output min. max. min. max. unit oe byte 0C3 d d u u data 0C31 0706ns oe sc d d u u sc 0C7 0706ns 2584 tbl 70 2584 tbl 72 to output from input sc 0? data 0?1 error error mult error mult error unit data 0C31 (3) 11 14 (2) 10 11 ns cb 0C7 (code id 1,0 = 00, 11) 9 12 7 9 ns cb 0C7 (code id 1,0 = 10) 9 10 ns le out / generate u u 9 d d 7 d d 8ns d d 13 u u 7 u u 8ns correct not internal control mode 11 ns diag mode not internal control mode 11 18 8 14 ns code id 1,0 13 (6) 17 12 15 ns le in from latched to transparent 16 19 13 16 ns le diag from latched to transparent u u 11 (6) 17 11 13 ns internal control le diag (internal control mode) from latched to transparent u u 11 (6) 16 11 13 ns mode data 0C31 (internal control mode) via diagnostic latch u u 11 17 (2) 911ns from input to input (latching data) set-up time min. hold time min. unit data 0C31 (4) d d le in 33ns cb 0C7 (4) d d le in 23ns data 0C31 (4, 6) d d le out / generate 5 (15) 0ns cb 0C7 (code id 00, 11) (4, 6) d d le out / generate 11 0 ns cb 0C7 (code id 10) (4, 6) d d le out / generate 60ns correct (4, 6) u u d d le out / generate 60ns diag mode (4, 6) d d le out / generate 13 0 ns code id 1,0 (4, 6) d d le out / generate 80ns le in (4, 6) u u d d le out / generate 14 0 ns data 0C31 (4, 6) le diag 33ns
11.6 19 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges minimum pulse widths min. le in , le out / generate , le diag ud ud (positiveCgoing pulse) 5 ns 2584 tbl 30 note: (15) above applies to correction path. 2584 tbl 29 idt49c460d ac electrical characteristics (guaranteed commercial range performance) temperature range: 0 c to +70 c, v cc = 5.0v 5% the inputs switch between 0v to 3v with signal measured at the 1.5v level. propagation delays (1) 2584 tbl 28 set-up and hold times relative to latch enables notes: 2584 tbl 31 1. ci = 50pf. 2. these parameters are combinational propagation delay calculations, and are not tested in production. 3. data in or correct data out measurement requires timing as shown in the switching waveforms. 4. set-up and hold times relative to latch enables (latching data). 5. output tests specified with ci = 5pf and measured to 0.5v change of output level. testing is performed at ci = 50pf and correlated to ci = 5pf. 6. not production tested, guaranteed by characterization. enable disable from input enable disable to output min. max. min. max. unit oe byte 0C3 d d u u data 0C31 0 8 0 10 ns oe sc d d u u sc 0C7 0 8 0 10 ns output enable/disable times (5) (6) to output from input sc 0? data 0?1 error error mult error mult error unit data 0C31 (3) 14 18 (2) 12 15 ns cb 0C7 (code id 1,0 = 00, 11) 11 16 10 12 ns cb 0C7 (code id 1,0 = 10) 12 12 ns le out / generate u u 9 d d 7 d d 8ns d d 14 u u 7 u u 8ns correct not internal control mode 12 ns diag mode not internal control mode 12 20 10 15 ns code id 1,0 14 (6) 18 13 16 ns le in from latched to transparent 17 21 14 17 ns le diag from latched to transparent u u 12 (6) 18 12 14 ns internal control le diag (internal control mode) from latched to transparent u u 12 (6) 17 12 14 ns mode data 0C31 (internal control mode) via diagnostic latch u u 12 19 (2) 10 12 ns from input to input (latching data) set-up time min. hold time min. unit data 0C31 (4) d d le in 33ns cb 0C7 (4) d d le in 23ns data 0C31 (4, 6) d d le out / generate 5 (15) 0ns cb 0C7 (code id 00, 11) (4, 6) d d le out / generate 11 0 ns cb 0C7 (code id 10) (4, 6) d d le out / generate 60ns correct (4, 6) u u d d le out / generate 60ns diag mode (4, 6) d d le out / generate 13 0 ns code id 1,0 (4, 6) d d le out / generate 80ns le in (4, 6) u u d d le out / generate 14 0 ns data 0C31 (4, 6) le diag 33ns
11.6 20 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges output enable/disable times (5) idt49c460d ac electrical characteristics (guaranteed military range performance) temperature range: C55 c to +125 c, v cc = 5.0v 10% the inputs switch between 0v to 3v with signal measured at the 1.5v level. propagation delays (1) 2584 tbl 32 set-up and hold times relative to latch enables notes: 2584 tbl 35 1. ci = 50pf. 2. these parameters are combinational propagation delay calculations, and are not tested in production. 3. data in or correct data out measurement requires timing as shown in the switching waveforms. 4. set-up and hold times relative to latch enables (latching data). 5. output tests specified with ci = 5pf and measured to 0.5v change of output level. testing is performed at ci = 50pf and correlated to ci = 5f. 6. not production tested, guaranteed by characterization. note : (15) above applies to correction path. 2584 tbl 33 enable disable from input enable disable to output min. max. min. max. unit oe byte 0C3 d d u u data 0C31 0 10 0 12 ns oe sc d d u u sc 0C7 0 10 0 12 ns minimum pulse widths min. le in , le out / generate , le diag ud ud (positiveCgoing pulse) 5 ns 2584 tbl 34 (6) to output from input sc 0? data 0?1 error error mult error mult error unit data 0C3 (3) 17 22 (2) 16 18 ns cb 0C7 (code id 1,0 = 00, 11) 13 17 12 14 ns cb 0C7 (code id 1,0 = 10) 13 14 ns le out / generate u u 10 d d 8 d d 8ns d d 15 u u 8 u u 9ns correct not internal control mode 13 ns diag mode not internal control mode 14 22 12 17 ns code id 1,0 16 (6) 20 15 18 ns le in from latched to transparent 18 24 16 19 ns le diag from latched to transparent u u 14 (6) 20 13 16 ns internal control le diag from latched to transparent u u 14 (6) 19 14 16 ns mode data 0C31 via diagnostic latch u u 14 22 (2) 11 14 ns from input to input (latching data) set-up time min. hold time min. unit data 0C31 (4) d d le in 33ns cb 0C7 (4) d d le in 23ns data 0C31 (4, 6) d d le out / generate 6 (15) 0ns cb 0C7 (code id 00, 11) (4, 6) d d le out / generate 12 0 ns cb 0C7 (code id 10) (4, 6) d d le out / generate 80ns correct (4, 6) u u d d le out / generate 70ns diag mode (4, 6) d d le out / generate 14 0 ns code id 1,0 (4, 6) d d le out / generate 90ns le in (4, 6) u u d d le out / generate 16 0 ns data 0C31 (4, 6) le diag 33ns
11.6 21 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges idt49c460c ac electrical characteristics (guaranteed commercial range performance) temperature range: 0 c to +70 c, v cc = 5.0v 5% the inputs switch between 0v to 3v with signal measured at the 1.5v level. propagation delays (1) 2584 tbl 36 set-up and hold times relative to latch enables output enable/disable times (5) notes: 2584 tbl 39 1. ci = 50pf. 2. these parameters are combinational propagation delay calculations, and are not tested in production. 3. data in or correct data out measurement requires timing as shown in the switching waveforms. 4. set-up and hold times relative to latch enables (latching data). 5. output tests specified with ci = 5pf and measured to 0.5v change of output level. testing is performed at ci = 50pf and correlated to ci = 5pf. 6. not production tested, guaranteed by characterization. note : (16) above applies to correction path. 2584 tbl 37 enable disable from input enable disable to output min. max. min. max. unit oe byte 0C3 d d u u data 0C31 0 10 0 12 ns oe sc d d u u sc 0C7 0 10 0 12 ns minimum pulse widths min. le in , le out / generate , le diag ud ud (positiveCgoing pulse) 6 ns 2584 tbl 38 (6) to output from input sc 0? data 0?1 error error mult error mult error unit data 0C31 (3) 19 24 (2) 16 20 ns cb 0C7 (code id 1,0 = 00, 11) 14 21 12 16 ns cb 0C7 (code id 1,0 = 10) 14 16 ns le out / generate u u 12 d d 9 d d 11 ns d d 18 u u 9 u u 11 ns correct not internal control mode 16 ns diag mode not internal control mode 16 26 11 20 ns code id 1,0 18 (6) 23 17 21 ns le in from latched to transparent 22 28 (2) 19 22 ns le diag from latched to transparent u u 15 (6) 24 15 19 ns internal control le diag from latched to transparent u u 16 (6) 22 15 18 ns mode data 0C31 via diagnostic latch u u 15 25 (2) 13 16 ns from input to input (latching data) set-up time min. hold time min. unit data 0C31 (4) d d le in 34ns cb 0C7 (4) d d le in 24ns data 0C31 (4, 6) d d le out / generate 6 (16) 0ns cb 0C7 (code id 00, 11) (4, 6) d d le out / generate 14 0 ns cb 0C7 (code id 10) (4, 6) d d le out / generate 80ns correct (4, 6) u u d d le out / generate 80ns diag mode (4, 6) d d le out / generate 17 0 ns code id 1,0 (4, 6) d d le out / generate 10 0 ns le in (4, 6) u u d d le out / generate 19 0 ns data 0C31 (4, 6) le diag 33ns
11.6 22 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges idt49c460c ac electrical characteristics (guaranteed military range performance) temperature range: C55 c to +125 c, v cc = 5.0v 10% the inputs switch between 0v to 3v with signal measured at the 1.5v level. propagation delays (1) 2584 tbl 40 set-up and hold times relative to latch enables output enable/disable times (5) notes: 2584 tbl 43 1. ci = 50pf. 2. these parameters are combinational propagation delay calculations, and are not tested in production. 3. data in or correct data out measurement requires timing as shown in the switching waveforms. 4. set-up and hold times relative to latch enables (latching data). 5. output tests specified with ci = 5pf and measured to 0.5v change of output level. testing is performed at ci = 50pf and correlated to ci = 5f. 6. not production tested, guaranteed by characterization. note: (19) above applies to correction path. 2584 tbl 41 enable disable from input enable disable to output min. max. min. max. unit oe byte 0C3 d d u u data 0C31 0 12 0 14 ns oe sc d d u u sc 0C7 0 12 0 14 ns minimum pulse widths min. le in , le out / generate , le diag ud ud (positiveCgoing pulse) 6 ns 2584 tbl 42 (6) to output from input sc 0? data 0?1 error error mult error mult error unit data 0C31 (3) 22 29 (2) 21 24 ns cb 0C7 (code id 1,0 = 00, 11) 17 23 16 18 ns cb 0C7 (code id 1,0 = 10) 17 18 ns le out / generate u u 13 d d 10 d d 12 ns d d 20 u u 10 u u 12 ns correct not internal control mode 17 ns diag mode not internal control mode 18 29 12 23 ns code id 1,0 21 (6) 26 20 24 ns le in from latched to transparent 24 32 21 25 ns le diag from latched to transparent u u 18 (6) 27 17 21 ns internal control le diag from latched to transparent u u 19 (6) 25 18 21 ns mode data 0C31 via diagnostic latch u u 18 29 (2) 14 18 ns from input to input (latching data) set-up time min. hold time min. unit data 0C31 (4) d d le in 34ns cb 0C7 (4) d d le in 24ns data 0C31 (4, 6) d d le out / generate 7 (19) 3ns cb 0C7 (code id 00, 11) (4, 6) d d le out / generate 16 0 ns cb 0C7 (code id 10) (4, 6) d d le out / generate 10 0 ns correct (4, 6) u u d d le out / generate 90ns diag mode (4, 6) d d le out / generate 19 0 ns code id 1,0 (4, 6) d d le out / generate 12 0 ns le in (4, 6) u u d d le out / generate 21 0 ns data 0C31 (4, 6) le diag 33ns
11.6 23 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges idt49c460b ac electrical characteristics (guaranteed commercial range performance) temperature range: 0 c to +70 c, v cc = 5.0v 5% the inputs switch between 0v to 3v with signal measured at the 1.5v level. propagation delays (1) 2584 tbl 44 set-up and hold times relative to latch enables 2584 tbl 45 output enable/disable times (5) notes: 2584 tbl 47 1. ci = 50pf. 2. these parameters are combinational propagation delay calculations, and are not tested in production. 3. data in or correct data out measurement requires timing as shown in the switching waveforms. 4. set-up and hold times relative to latch enables (latching data). 5. output tests specified with ci = 5pf and measured to 0.5v change of output level. testing is performed at ci = 50pf and correlated to ci = 5pf. 6. not production tested, guaranteed by characterization. enable disable from input enable disable to output min. max. min. max. unit oe byte 0C3 d d u u data 0C31 0 12 0 14 ns oe sc d d u u sc 0C7 0 12 0 14 ns minimum pulse widths min. le in , le out / generate , le diag ud ud (positiveCgoing pulse) 9 ns 2584 tbl 46 to output from input sc 0? data 0?1 error error mult error mult error unit data 0C31 (3) 25 30 (2) 25 27 ns cb 0C7 (code id 1,0 = 00, 11) 14 30 17 20 ns cb 0C7 (code id 1,0 = 10) 16 18 ns le out / generate u u 12 d d 23 d d 23 ns d d 21 u u 23 u u 23 ns correct not internal control mode 23 ns diag mode not internal control mode 17 26 20 24 ns code id 1,0 18 (6) 26 21 26 ns le in from latched to transparent 27 38 (2) 30 3 ns le diag from latched to transparent u u 15 (6) 29 19 22 ns internal control le diag from latched to transparent u u 16 (6) 32 19 24 ns mode data 0C31 via diagnostic latch u u 16 32 (2) 20 25 ns from input to input (latching data) set-up time min. hold time min. unit data 0C31 (4) d d le in 44ns cb 0C7 (4) d d le in 44ns data 0C31 (4, 6) d d le out / generate 19 0 ns cb 0C7 (code id 00, 11) (4, 6) d d le out / generate 15 0 ns cb 0C7 (code id 10) (4, 6) d d le out / generate 15 0 ns correct (4, 6) u u d d le out / generate 11 0 ns diag mode (4, 6) d d le out / generate 17 0 ns code id 1,0 (4, 6) d d le out / generate 17 0 ns le in (4, 6) u u d d le out / generate 20 0 ns data 0C31 (4, 6) le diag 43ns
11.6 24 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges 2584 tbl 48 set-up and hold times relative to latch enables 2584 tbl 49 output enable/disable times (5) notes: 2584 tbl 51 1. ci = 50pf. 2. these parameters are combinational propagation delay calculations, and are not tested in production. 3. data in or correct data out measurement requires timing as shown in the switching waveforms. 4. set-up and hold times relative to latch enables (latching data). 5. output tests specified with ci = 5pf and measured to 0.5v change of output level. testing is performed at ci = 50pf and correlated to ci = 5pf. 6. not production tested, guaranteed by characterization. enable disable from input enable disable to output min. max. min. max. unit oe byte 0C3 d d u u data 0C31 0 12 0 14 ns oe sc d d u u sc 0C7 0 12 0 14 ns minimum pulse widths min. le in , le out / generate , le diag ud ud (positiveCgoing pulse) 12 ns 2584 tbl 50 idt49c460b ac electrical characteristics (guaranteed military range performance) temperature range: C55 c to +125 c, v cc = 5.0v 10% the inputs switch between 0v to 3v with signal measured at the 1.5v level. propagation delays (1) to output from input sc 0? data 0?1 error error mult error mult error unit data 0C31 (3) 28 33 (2) 28 30 ns cb 0C7 (code id 1,0 = 00, 11) 17 33 20 23 ns cb 0C7 (code id 1,0 = 10) 19 23 ns le out / generate u u 15 d d 26 d d 26 ns d d 24 u u 26 u u 26 ns correct not internal control mode 26 ns diag mode not internal control mode 20 29 23 27 ns code id 1,0 21 29 24 29 ns le in from latched to transparent 30 41 33 36 ns le diag from latched to transparent u u 18 32 22 25 ns internal control le diag from latched to transparent u u 19 35 22 27 ns mode data 0C31 via diagnostic latch u u 19 35 (2) 23 28 ns from input to input (latching data) set-up time min. hold time min. unit data 0C31 (4) d d le in 44ns cb 0C7 (4) d d le in 44ns data 0C31 (4, 6) d d le out / generate 23 0 ns cb 0C7 (code id 00, 11) (4, 6) d d le out / generate 18 0 ns cb 0C7 (code id 10) (4, 6) d d le out / generate 18 0 ns correct (4, 6) u u d d le out / generate 14 0 ns diag mode (4, 6) d d le out / generate 20 0 ns code id 1,0 (4, 6) d d le out / generate 20 0 ns le in (4, 6) u u d d le out / generate 23 0 ns data 0C31 (4, 6) le diag 43ns
11.6 25 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges 2584 tbl 52 set-up and hold times relative to latch enables 2584 tbl 53 output enable/disable times (5) notes: 2584 tbl 55 1. ci = 50pf. 2. these parameters are combinational propagation delay calculations, and are not tested in production. 3. data in or correct data out measurement requires timing as shown in the switching waveforms. 4. set-up and hold times relative to latch enables (latching data). 5. output tests specified with ci = 5pf and measured to 0.5v change of output level. testing is performed at ci = 50pf and correlated to ci = 5pf. 6. not production tested, guaranteed by characterization. enable disable from input enable disable to output min. max. min. max. unit oe byte 0C3 d d u u data 0C31 0 12 0 14 ns oe sc d d u u sc 0C7 0 12 0 14 ns minimum pulse widths min. le in , le out / generate , le diag ud ud (positiveCgoing pulse) 9 ns 2584 tbl 54 idt49c460a ac electrical characteristics (guaranteed commercial range performance) temperature range: 0 c to 70 c, v cc = 5.0v 5% the inputs switch between 0v to 3v with signal measured at the 1.5v level. propagation delays (1) to output from input sc 0? data 0?1 error error mult error mult error unit data 0C31 (3) 27 36 (2) 30 33 ns cb 0C7 (code id 1,0 = 00, 11) 16 34 19 23 ns cb 0C7 (code id 1,0 = 10) 16 20 ns le out / generate u u 12 d d 25 d d 25 ns d d 21 u u 25 u u 25 ns correct not internal control mode 23 ns diag mode not internal control mode 17 26 20 24 ns code id 1,0 18 26 21 26 ns le in from latched to transparent 27 38 30 33 ns le diag from latched to transparent u u 15 29 19 22 ns internal control le diag from latched to transparent u u 16 32 29 24 ns mode data 0C31 via diagnostic latch u u 16 32 (2) 20 25 ns from input to input (latching data) set-up time min. hold time min. unit data 0C31 (4) d d le in 54ns cb 0C7 (4) d d le in 54ns data 0C31 (4, 6) d d le out / generate 23 0 ns cb 0C7 (code id 00, 11) (4, 6) d d le out / generate 15 0 ns cb 0C7 (code id 10) (4, 6) d d le out / generate 15 0 ns correct (4, 6) u u d d le out / generate 11 0 ns diag mode (4, 6) d d le out / generate 17 0 ns code id 1,0 (4, 6) d d le out / generate 17 0 ns le in (4, 6) u u d d le out / generate 25 0 ns data 0C31 (4, 6) le diag 53ns
11.6 26 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges idt49c460a ac electrical characteristics (guaranteed military range performance) temperature range: C55 c to +125 c, v cc = 5.0v 10% the inputs switch between 0v to 3v with signal measured at the 1.5v level. propagation delays (1) 2584 tbl 56 set-up and hold times relative to latch enables 2584 tbl 57 enable disable from input enable disable to output min. max. min. max. unit oe byte 0C3 d d u u data 0C31 0 12 0 14 ns oe sc d d u u sc 0C7 0 12 0 14 ns output enable/disable times (5) 2584 tbl 58 minimum pulse widths min. le in , le out / generate , le diag ud ud (positiveCgoing pulse) 12 ns notes: 2584 tbl 59 1. ci = 50pf. 2. these parameters are combinational propagation delay calculations, and are not tested in production. 3. data in or correct data out measurement requires timing as shown in the switching waveforms. 4. set-up and hold times relative to latch enables (latching data). 5. output tests specified with ci = 5pf and measured to 0.5v change of output level. testing is performed at ci = 50pf and correlated to ci = 5pf. 6. not production tested, guaranteed by characterization. to output from input sc 0? data 0?1 error error mult error mult error unit data 0C31 (3) 30 39 (2) 33 36 ns cb 0C7 (code id 1,0 = 00, 11) 19 37 22 26 ns cb 0C7 (code id 1,0 = 10) 19 23 ns le out / generate u u 15 d d 28 d d 28 ns d d 24 u u 28 u u 28 ns correct not internal control mode 26 ns diag mode not internal control mode 20 29 23 27 ns code id 1,0 21 29 24 29 ns le in from latched to transparent 30 41 33 36 ns le diag from latched to transparent u u 18 32 22 25 ns internal control le diag from latched to transparent u u 19 35 22 27 ns mode data 0C31 via diagnostic latch u u 19 35 (2) 23 28 ns from input to input (latching data) set-up time min. hold time min. unit data 0C3 (4) d d le in 54ns cb 0C7 (4) d d le in 54ns data 0C31 (4, 6) d d le out / generate 27 0 ns cb 0C7 (code id 00, 11) (4, 6) d d le out / generate 18 0 ns cb 0C7 (code id 10) (4, 6) d d le out / generate 18 0 ns correct (4, 6) u u d d le out / generate 14 0 ns diag mode (4, 6) d d le out / generate 20 0 ns code id 1,0 (4, 6) d d le out / generate 20 0 ns le in (4, 6) u u d d le out / generate 28 0 ns data 0C31 (4, 6) le diag 53ns
11.6 27 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges idt49c460 ac electrical characteristics (guaranteed commercial range performance) temperature range: 0 c to +70 c, v cc = 5.0v 5% the inputs switch between 0v to 3v with signal measured at the 1.5v level. propagation delays (1) 2584 tbl 60 set-up and hold times relative to latch enables output enable/disable times (5) notes: 2584 tbl 63 1. ci = 50pf. 2. these parameters are combinational propagation delay calculations, and are not tested in production. 3. data in or correct data out measurement requires timing as shown in the switching waveforms. 4. set-up and hold times relative to latch enables (latching data). 5. output tests specified with ci = 5pf and measured to 0.5v change of output level. testing is performed at ci = 50pf and correlated to ci = 5pf. 6. not production tested, guaranteed by characterization. 2584 tbl 61 enable disable from input enable disable to output min. max. min. max. unit oe byte 0C3 d d u u data 0C31 0 15 0 17 ns oe sc d d u u sc 0C7 0 15 0 17 ns minimum pulse widths min. le in , le out / generate , le diag ud ud (positiveCgoing pulse) 12 ns to output from input sc 0? data 0?1 error error mult error mult error unit data 0C31 (3) 37 49 (2) 40 45 ns cb 0C7 (code id 1,0 = 00, 11) 22 46 26 31 ns cb 0C7 (code id 1,0 = 10) 22 30 ns le out / generate u u 17 d d 30 d d 30 ns d d 29 u u 30 u u 30 ns correct not internal control mode 31 ns diag mode not internal control mode 23 35 27 33 ns code id 1,0 25 35 29 35 ns le in from latched to transparent 37 51 41 45 ns le diag from latched to transparent u u 21 38 26 30 ns internal control le diag from latched to transparent u u 22 42 26 33 ns mode data 0C31 via diagnostic latch u u 22 42 (2) 27 34 ns from input to input (latching data) set-up time min. hold time min. unit data 0C31 (4) d d le in 64ns cb 0C7 (4) d d le in 54ns data 0C31 (4, 6) d d le out / generate 30 0 ns cb 0C7 (code id 00, 11) (4, 6) d d le out / generate 20 0 ns cb 0C7 (code id 10) (4, 6) d d le out / generate 20 0 ns correct (4, 6) u u d d le out / generate 16 0 ns diag mode (4, 6) d d le out / generate 23 0 ns code id 1,0 (4, 6) d d le out / generate 23 0 ns le in (4, 6) u u d d le out / generate 31 0 ns data 0C31 (4, 6) le diag 63ns 2584 tbl 62
11.6 28 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges idt49c460 ac electrical characteristics (guaranteed military range performance) temperature range: C55 c to +125 c, v cc = 5.0v 10% the inputs switch between 0v to 3v with signal measured at the 1.5v level. propagation delays (1) output enable/disable times (5) enable disable from input enable disable to output min. max. min. max. unit oe byte 0C3 d d u u data 0C31 0 15 0 17 ns oe sc d d sc 0C7 0 15 0 17 ns 2584 tbl 64 set-up and hold times relative to latch enables 2584 tbl 65 minimum pulse widths min. le in , le out / generate , le diag (positiveCgoing pulse) 15 ns notes: 2584 tbl 67 1. ci = 5pf. 2. these parameters are combinational propagation delay calculations, and are not tested in production. 3. data in or correct data out measurement requires timing as shown in the switching waveforms. 4. set-up and hold times relative to latch enables (latching data). 5. output tests specified with ci = 5pf and measured to 0.5v change of output level. testing is performed at ci = 50pf and correlated to ci = 5pf. 6. not production tested, guaranteed by characterization. to output from input sc 0? data 0?1 error error mult error mult error unit data 0C31 (3) 40 52 (2) 44 48 ns cb 0C7 (code id 1,0 = 00, 11) 25 49 29 34 ns cb 0C7 (code id 1,0 = 10) 25 33 ns le out / generate u u 20 d d 33 d d 33 ns d d 32 u u 33 u u 33 ns correct not internal control mode 34 ns diag mode not internal control mode 26 38 30 36 ns code id 1,0 28 38 32 38 ns le in from latched to transparent 40 54 44 48 ns le diag from latched to transparent u u 24 42 29 33 ns internal control le diag from latched to transparent u u 25 47 (2) 29 36 ns mode data 0C31 via diagnostic latch u u 25 47 30 37 ns from input to input (latching data) set-up time min. hold time min. unit data 0C31 (4) d d le in 64ns cb 0C7 (4) d d le in 54ns data 0C31 (4, 6) d d le out / generate 36 0 ns cb 0C7 (code id 00, 11) (4, 6) d d le out / generate 24 0 ns cb 0C7 (code id 10) (4, 6) d d le out / generate 24 0 ns correct (4, 6) u u d d le out / generate 20 0 ns diag mode (4, 6) d d le out / generate 28 0 ns code id 1,0 (4, 6) d d le out / generate 28 0 ns le in (4, 6) u u d d le out / generate 37 0 ns data 0C31 (4, 6) le diag 63ns 2584 tbl 66
11.6 29 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges detect or correction mode (from generate mode) notes: 2584 drw 10 1. bold indicates critical parameters. 2. this is "e" version timing spec. check appropriate table for other speed versions. * assumes "cb in " and/or "data in " are valid at least 4ns before "le in " goes high. le in . correct cb in data bus oe byte oe byte = high to data out disabled oe byte = high to data out disabled oe byte = low to data out enabled oe byte = low to data out enabled data in to data out max. max. max. min. max. min. max. max. propagation delay from to min./max. oe sc = high to sc out disabled oe sc = high to sc out disabled oe sc = low to sc out enabled oe sc = low to sc out enabled sc out oe sc (syndrome bits come out) min. max. min. max. (corrected data if correct mode) (data in if detect mode) correct = high to data out cb in to data out cb in to data out *le in = high to data out le out / gen = high to data out le out / gen = high to merror = low le out / gen = high to error = low data in to error error = low cb in to error = low *le in = high to error = low* (low = error) data in to merror = low cb in to merror = low *le in = high to merror = low* (low = error) data in to sc out cb in to sc out max. max. max. max. max. max. max. max. max. max. max. max. le out / gen error merror 14 7 0 0 6 valid data valid checkbits in out (output) 7 0 0 6 valid 9 11 16* 9 11 13* 7 10 7 8 9 19* 10 12 11 code id1,0 = 00, 11 code id1,0 = 00, 11 code id1,0 = 10 in
11.6 30 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges generate mode (from detect or correction mode) notes: 1. bold indicates critical parameters. 2. valiid "data" and valid cb in " are shown to occur simultaneously, since both buses are latched and opened by the "le in " input. 3. this is "e" version timing spec. check appropriate table for other speed versions. * assumes data bus becomes input 4ns before le in goes high. oe sc = high to sc out disabled oe sc = high to sc out disabled oe sc = low to sc out enabled oe sc = low to sc out enabled correct sc out oe sc err/merr le out / gen le in cb in data bus oe byte oe byte = high to data out disabled oe byte = high to data out disabled oe byte = low to data out enabled oe byte = low to data out enabled cb in to data out le out / generate = low to error = high le out / generate = low to sc out data in to sc out *le in = high to sc out * cb in to sc out (forced high) (check bits exit) (don't care) min. max. min. max. min. max. min. max. max. max. max. max. max. max. propagation delay from to min./max. 2584 drw 09 7 0 0 6 9 16* 11 13 7 10 7 0 0 6 valid checkbits in code id 1,0 = 10 (generate mode) (code id 1,0 = 10) valid checkbits valid data out (output) in
11.6 31 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges set-up and hold times and minimum pulse widths notes: 2584 drw 11 1. bold indicates critical parameters. 2. this is "e" version timing spec. check appropriate table for other speed versions. * enable to enable timing requirement to ensure that the last data word applied to "data in " is made available as data out "; assumes that "data in " is valid at least 4ns before "le in " goes high. correct data in cb in cb in set-up to le in = low cb in hold to le in = low min. min. set-up/hold time of with respect to min./max. *le in = high to le out / gen = low* data set-up to le in = low data hold to le in = low cb in set-up to le out / gen = low cb in set-up to le out / gen = low data set-up to le out / gen = low min. min. le out / gen le in width le out / generate width correct set-up to le out / gen = low min. min. min. min. min. min. min. le in . valid code id1,0 = 00, 11 code id1,0 = 10 3 5 14* 3 3 11 6 6 6 5 2 valid i ol outputs i oh v cc 2584 drw 13 2584 drw 12 figure 5. input structure (all inputs) figure 6. out put structure esd protection i il inputs i ih input/output interface circuit
11.6 32 idt49c460/a/b/c/d/e 32-bit cmos error detection and correction unit military and commercial temperature ranges test load circuit 2584 drw 14 definitions: c l = load capacitance: includes jig and probe capacitance r l = termination resistance: should be equal to z out of the pulse generator figure 7. vout 50pf cl 500 w + 7.0v 500 w d.u.t. vcc vin rt pulse generator ordering information idt 49c460 device type x speed x package x process/ temperature range blank b g j ff blank a b c d e commercial (0 c to + 70 c) military (C 55 c to + 125 c) compliant to mil-std-883, class b pin grid array plastic leaded chip carrier fine pitch flatpack standard speed high-speed very high-speed super-high-speed ultra-high speed fastest speed 49c460 32-bit e. d. c. 2584 drw 15 ac test conditions input pulse levels gnd to 3.0v input rise/fall times 1v/ns input timing reference levels 1.5v output reference levels 1.5v output load see figure 7 2584 tbl 69 test switch disable low closed enable low all other tests open 2584 tbl 68

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